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100329 Low Power Octal ECL/TTL Bidirectional Translator with Register
August 1989 Revised August 2000
100329 Low Power Octal ECL/TTL Bidirectional Translator with Register
General Description
The 100329 is an octal registered bidirectional translator designed to convert TTL logic levels to 100K ECL logic levels and vice versa. The direction of the translation is determined by the DIR input. A LOW on the output enable input (OE) holds the ECL outputs in a cut-off state and the TTL outputs at a high impedance level. The outputs change synchronously with the rising edge of the clock input (CP) even though only one output is enabled at the time. The cut-off state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-followers to turn off when the termination supply is -2.0V, presenting a high impedance to the data bus. This high impedance reduces the termination power and prevents loss of low state noise margin when several loads share the bus. The 100329 is designed with FAST TTL output buffers, featuring optimal DC drive and capable of quickly charging and discharging highly capacitive loads. All inputs have 50 k pull-down resistors.
Features
s Bidirectional translation s ECL high impedance outputs s Registered outputs s FAST TTL outputs s 3-STATE outputs s Voltage compensated operating range = -4.2V to -5.7V s High drive IOS
Ordering Code:
Order Number 100329PC 100329QC 100329QI Package Number N24E V28A V28A Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (-40C to +85C)
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagrams
24-Pin DIP 28-Pin PLCC
FAST is a registered trademark of Fairchild Semiconductor Corporation.
(c) 2000 Fairchild Semiconductor Corporation
DS010583
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100329
Logic Symbol
Functional Diagram
Pin Descriptions
Pin Names E0-E7 T0-T7 OE CP DIR TTL Data I/O Output Enable Input Clock Pulse Input (Active Rising Edge) Direction Control Input Description ECL Data I/O
All pins function at 100K ECL levels except for T0-T7.
Truth Table
OE L L H H H H H H DIR L H L L L H H H CP X X ECL Port Input LOW (Cut-Off) L H X L H NC L H NC L H X (Note 1) (Note 1) (Note 1)(Note 3) (Note 2) (Note 2) (Note 2)(Note 3)
Note: DIR and OE use ECL logic levels
TTL Port Z
Notes (Note 1)(Note 3)
Input (Note 2)(Note 3)

L L
H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance = LOW-to-HIGH Clock Transition NC = No Change
Detail
Note 1: ECL input to TTL output mode. Note 2: TTL input to ECL output mode. Note 3: Retains data present before CP.
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Absolute Maximum Ratings(Note 4)
Storage Temperature (TSTG) VEE Pin Potential to Ground Pin VTTL Pin Potential to Ground Pin ECL Input Voltage (DC) ECL Output Current (DC Output HIGH) TTL Input Voltage (Note 6) TTL Input Current (Note 6) Voltage Applied to Output in HIGH State 3-STATE Output Current Applied to TTL Output in LOW State (Max) ESD (Note 5) twice the rated IOL (mA)
-65C to +150C -7.0V to +0.5V -0.5V to +6.0V
VEE to +0.5V
Recommended Operating Conditions
Case Temperature (TC) ECL Supply Voltage (VEE) TTL Supply Voltage (VTTL) 0C to +85C
Maximum Junction Temperature (Tj) +150C
-5.7V to -4.2V +4.5V to +5.5V
-50 mA -0.5V to +6.0V -30 mA to +5.0 mA
Note 4: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 5: ESD testing conforms to MIL-STD-883, Method 3015. Note 6: Either voltage limit or current limit is sufficient to protect inputs.
-0.5V to +5.5V
2000V
TTL-to-ECL DC Electrical Characteristics
VEE = -4.2V to -5.7V, VCC = VCCA = GND, TC = 0C to +85C, VTTL = +4.5V to +5.5V (Note 7) Symbol Parameter Min Typ Max Units VOH VOL Output HIGH Voltage Output LOW Voltage Cutoff Voltage -2000 VOHC VOLC VIH VIL IIH IIL VFCD IEE Output HIGH Voltage Corner Point HIGH Output LOW Voltage Corner Point LOW Input HIGH Voltage Input LOW Voltage Input HIGH Current Breakdown Test Input LOW Current Input Clamp Diode Voltage VEE Supply Current -189 -199 -94 -94 mA -700 -1.2 2.0 0 -1950 mV mV VIN = VIH (Min) or VIL (Max) -1610 5.0 0.8 70 1.0 mV V V A mA A V Loading with 50 to -2V Over VTTL, V EE, TC Range Over VTTL, V EE, TC Range VIN = +2.7V VIN = +5.5V VIN = +0.5V IIN = -18 mA LE LOW, OE and DIR HIGH Inputs Open VEE = -4.2V to -4.8V VEE = -4.2V to -5.7V -1025 -1830 -955 -1705 -870 -1620 mV mV Conditions VIN = VIH (Max) or VIL (Min) Loading with 50 to -2V OE or DIR LOW, VIN = VIH (Max) or VIL (Min) Loading with 50 to -2V -1035
Note 7: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under "worst case" conditions.
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100329
ECL-to-TTL DC Electrical Characteristics
VEE = -4.2V to -5.7V, VCC = VCCA = GND, TC = 0C to +85C, CL = 50 pF, VTTL = +4.5V to +5.5V (Note 8) Symbol Parameter Min Typ Max Units Conditions VOH VOL VIH VIL IIH IIL IOZHT IOZLT IOS ITTL Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current 3-STATE Current Output HIGH 3-STATE Current Output LOW Output Short-Circuit Current VTTL Supply Current 74 49 67 mA mA mA TTL Outputs LOW TTL Outputs HIGH TTL Outputs in 3-STATE -225 -100 mA VOUT = 0.0V, VTTL = +5.5V -700 A VOUT = +0.5V 0.50 70 -1165 -1830 2.7 2.4 3.1 2.9 0.3 0.5 -870 -1475 350 V V V mV mV A A A IOH = -3 mA, VTTL = 4.75V IOH = -3 mA, VTTL = 4.50V IOL = 24 mA, VTTL = 4.50V Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VIN = VIH (Max) VIN = VIL (Min) VOUT = +2.7V
Note 8: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under "worst case" conditions.
DIP TTL-to-ECL AC Electrical Characteristics
VEE = -4.2V to -5.7V, VTTL = +4.5V to +5.5V, VCC = VCCA = GND TC = 0C TC = 25C Symbol Parameter Min Max Min Max fMAX tPLH tPHL tPZH tPHZ tPHZ tSET tHOLD tPW(H) tTLH tTHL OE to En (Cutoff to HIGH) OE to En (HIGH to Cutoff) DIR to En (HIGH to Cutoff) Tn to CP Tn to CP Pulse Width CP Transition Time 20% to 80%, 80% to 20% 1.1 1.7 2.1 0.6 1.6 1.1 1.7 2.1 0.6 1.6 1.1 1.9 2.1 0.6 1.6 ns ns ns ns Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 1.6 4.3 1.6 4.3 1.7 4.5 ns Figures 1, 2 1.5 4.5 1.6 4.5 1.6 4.6 ns Figures 1, 2 1.3 4.2 1.5 4.4 1.7 4.8 ns Figures 1, 2 Max Toggle Frequency CP to En 350 1.7 3.6 350 1.7 3.7 TC = 85C Min 350 1.9 3.9 Max Units MHz ns Figures 1, 2 Conditions
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100329
DIP ECL-to-TTL AC Electrical Characteristics
VEE = -4.2V to -5.7V, VTTL = +4.5V to +5.5V, VCC = VCCA = GND, CL = 50 pF TC = 0C TC = 25C Symbol Parameter Min Max Min Max fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tSET tHOLD tPW(H) OE to Tn (Enable Time) OE to Tn (Disable Time) DIR to Tn (Disable Time) En to CP En to CP Pulse Width CP 3.4 3.8 3.2 3.0 2.7 2.8 1.1 2.1 4.1 8.45 9.2 8.95 7.7 8.2 7.45 3.7 4.0 3.3 3.4 2.8 3.1 1.1 2.1 4.1 8.95 9.2 8.95 8.7 8.7 7.95 4.0 4.3 3.5 4.1 3.1 4.0 1.1 2.6 4.1 9.7 9.95 9.2 9.95 8.95 9.2 ns ns ns ns ns ns Figures 3, 5 Figures 3, 5 Figures 3, 6 Figures 3, 4 Figures 3, 4 Figures 3, 4 Max Toggle Frequency CP to Tn 125 3.1 7.2 125 3.1 7.2 TC = 85C Min 125 3.3 7.7 Max MHz ns Figures 3, 4 Units Conditions
PLCC and TTL-to-ECL AC Electrical Characteristics
VEE = -4.2V to -5.7V, VTTL = +4.5V to +5.5V Symbol fMAX tPLH tPHL tPZH tPHZ tPHZ tSET tHOLD tPW(H) tTLH tTHL tOSHL OE to En (Cutoff to HIGH) OE to En (HIGH to Cutoff) DIR to En (HIGH to Cutoff) Tn to CP Tn to CP Pulse Width CP Transition Time 20% to 80%, 80% to 20% Maximum Skew Common Edge Output-to-Output Variation Data to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation Data to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation Data to Output Path tPS Maximum Skew Pin (Signal) Transition Variation Data to Output Path
Note 9: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST ). Parameters tOST and tPS guaranteed by design.
Parameter Max Toggle Frequency CP to En
TC = 0C Min 350 1.7 1.3 1.5 1.6 1.0 1.7 2.0 0.6 1.6 3.4 4.0 4.3 4.1 Max
TC = 25C Min 350 1.7 1.5 1.6 1.6 1.0 1.7 2.0 0.6 1.6 3.5 4.2 4.3 4.1 Max
TC = 85C Min 350 1.9 1.7 1.6 1.7 1.0 1.9 2.0 0.6 1.6 3.7 4.6 4.4 4.3 Max
Units MHz ns ns ns ns ns ns ns ns
Conditions
Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 PLCC Only
200
200
200
ps
(Note 9) PLCC Only
200
200
200
ps
(Note 9) PLCC Only
650
650
650
ps
(Note 9) PLCC Only
650
650
650
ps
(Note 9)
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100329
PLCC and ECL-to-TTL AC Electrical Characteristics
VEE = -4.2V to -5.7V, VTTL = +4.5V to +5.5V, CL = 50 pF TC = 0C Symbol Parameter Min Max fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tSET tHOLD tPW(H) tOSHL OE to Tn (Enable Time) OE to Tn (Disable Time) DIR to Tn (Disable Time) En to CP En to CP Pulse Width CP Maximum Skew Common Edge Output-to-Output Variation Data to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation Data to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation Data to Output Path tPS Maximum Skew Pin (Signal) Transition Variation Data to Output Path
Note 10: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design.
TC = 25C Min 125 3.1 3.7 4.0 3.3 3.4 2.8 3.1 1.0 2.0 4.0 Max 7.0 8.75 9.0 8.75 8.5 8.5 7.75
TC = 85C Min 125 3.3 4.0 4.3 3.5 4.1 3.1 4.0 1.0 2.5 4.0 7.5 9.5 9.75 9.0 9.75 8.75 9.0 Max
Units MHz ns ns ns ns ns ns ns
Conditions
Max Toggle Frequency CP to Tn
125 3.1 3.4 3.8 3.2 3.0 2.7 2.8 1.0 2.0 4.0 600 7.0 8.25 9.0 8.75 7.5 8.0 7.25
Figures 3, 4 Figures 3, 5 Figures 3, 5 Figures 3, 6 Figures 3, 4 Figures 3, 4 Figures 3, 4 PLCC Only (Note 10) PLCC Only
600
600
ps
850
850
850
ps
(Note 10) PLCC Only
1350
1350
1350
ps
(Note 10) PLCC Only
950
950
950
ps
(Note 10)
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100329
Test Circuitry
(TTL-to-ECL)
Note 11: RT = 50 termination resistive load. When an input or output is being monitored by a scope, RTis supplied by the scope's 50 input resistance. When an input or output is not being monitored, an external 50 resistance must be applied to serve as RT. Note 12: TTL and ECL force signals are brought to the DUT via 50 coax lines. Note 13: VTTL is decoupled to ground with 0.1 F, VEE is decoupled to ground with 0.01 F and VCC is connected to ground.
FIGURE 1. TTL-to-ECL AC Test Circuit
Switching Waveforms
(TTL-to-ECL)
FIGURE 2. TTL to ECL Transition--Propagation Delay and Transition Times
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100329
Test Circuitry
(ECL-to-TTL)
Note 14: RT = 50 termination resistive load. When an input or output is being monitored by a scope, RT is supplied by the scope's 50 input resistance. When an input or output is not being monitored, an external 50 resistance must be applied to serve as RT. Note 15: The TTL 3-STATE pull-up switch is connected to +7V only for ZL and LZ tests. Note 16: TTL and ECL force signals are brought to the DUT via 50 coax lines. Note 17: VTTL is decoupled to ground with 0.1 F, VEE is decoupled to ground with 0.01 F and VCC is connected to ground.
FIGURE 3. ECL-to-TTL AC Test Circuit
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Switching Waveforms
(ECL-to-TTL)
Note: DIR is LOW, OE is HIGH
FIGURE 4. ECL-to-TTL Transition--Propagation Delay and Transition Times
Note: DIR is LOW
FIGURE 5. ECL-to-TTL Transition, OE to TTL Output, Enable and Disable Times
Note: OE is HIGH
FIGURE 6. ECL-to-TTL Transition, DIR to TTL Output, Disable Time
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100329
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E
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100329 Low Power Octal ECL/TTL Bidirectional Translator with Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 11 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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